NXP Semiconductors
Principal IP verification engineer
Employment
Full-timeFrom the employer
Full time
Level
PrincipalCategory
EngineeringCountry assessment
Not doable from Austria because it is tied to an office and never says it can be done remotely.
Our assessment is guidance. Confirm arrangements with the employer.
Job description
IP verification engineer - Principal
In this role you will be responsible for verifying complex IPs involving memory controllers, and interconnects, collaborating with global design and architecture teams.
Key responsibilities
- Develop and execute verification plans for memory controllers, interconnects and other infrastructural IPs
- Build scalable SystemVerilog/UVM-based verification environments with reusable UVM components (agents, monitors, scoreboards)
- Own end-to-end IP verification sign-off
- Achieve high-quality metrics including functional coverage and code coverage
- Manage regressions and debug failures
- Collaborate closely with design teams to resolve issues
Required expertise
Experience: 10+ years
- Strong experience in SystemVerilog, UVM, and Verilog
- Good understanding of Functional verification methodologies, Assertions (SVA) and coverage
- Good understanding of interconnect protocols such as AXI, AHB, CHI and PCIE
- Experience debugging complex RTL and testbench issues
- Experience in Formal verification is an added plus